The present invention relates to a nonvolatile semiconductor memory device having multi-storage nonvolatile memory cells in which one memory cell transistor can store information of at least two bits, and further to a semiconductor integrated circuit such as a microcomputer and the like containing the nonvolatile semiconductor memory device.
A typical nonvolatile semiconductor memory device having nonvolatile memory cells is an EEPROM (electrically erasable and programmable read only memory), which can electrically perform program in a byte unit, or a block electrically erasable flash memory.
Any of the nonvolatile semiconductor memory devices is utilized in memory cards which can be easily carried and in devices which can be operated from a remote site, and the like because they can hold memory information without the supply of power, and they act as a data storage, a program storage and the like to store information in a nonvolatile fashion as the initial setting of the operation of the device.
While nonvolatile semiconductor memory devices have been widely used in the filed of computers, communication equipment, controllers, OA (office automation) equipment, consumer equipment and so on, recently, they are particularly applied to portable communication equipment, IC cards used as bank terminals, image storing mediums of camera and the like. As the markets for them are expanded and the systems therefor are developed, a higher programming speed, high density, and high multi-function are required to the nonvolatile semiconductor memory devices.
A conventional nonvolatile semiconductor memory device, that is, a conventional EEPROM and a conventional flash memory will be compared with each other.
Since the memory cell of the EEPROM often includes of two transistors, that is, a memory transistor such as a MNOS and the like and a switch transistor, it is suitable for multi-function while it is not suitable for high density. In contrast, since the memory cell of the flash memory includes only one transistor, it is suitable for high density while it is not suitable for multi-function. Thus, it can be said that the EEPROM and the flash memory are separately used in a field in which they can be advantageously used from the structure thereof.
As to a programming speed, both the EEPROM and the flash memory conventionally require about milliseconds because both of them employ any of a tunnel programming method and a hot-carrier programming method. The programming speed is incommensurably long as compared with a processing time of about nanoseconds required by CPUs (central processing units).
Since a memory cell, which aims at the same direction as the gist of the present invention, has been proposed, the structure of a memory cell which corresponds to the structure of the above memory cell will be shown in FIGS. 3 to 5 and an operation bias of a memory cell array is shown in FIGS. 6 to 9, prior to the description of the memory cell which will be provided by the inventors. While the structure of the memory cell shown in FIGS. 3 to 5 was presented by Dr. Nissan-Cohen in the invited talk of xe2x80x9cSemiconductor Interface Specialist Conference: SISC, San Diegoxe2x80x9d, in December 1998, it is not recorded as a document at present. The overall structure of the memory cell was clarified to the attendants by Dr. Boaz Eitan in the invited talk of xe2x80x9cInternational Conference on Solid State Devices and Materials: SSDM, Tokyoxe2x80x9d, in September 1999 and the memory cell is called a NROM.
To describe the principle and operation of the memory, the memory includes one transistor type nonvolatile semiconductor memory including a gate insulating film having discrete traps, program is locally performed to the discrete traps by so-called hot carrier injection at a drain edge and read is performed utilizing charge trapped by the program as the source side of a transistor. That is, program and read are carried out by reversing a direction in which a current; flows to the memory transistor (reverse read) as shown in FIG. 3. More specifically, in the operation of the memory transistor, the function of a source line is interchanged with the function of a bit line between program and read. Further, since program is locally performed to the discrete traps as shown in FIG. 4, it is possible to provide another edge in the channel of the memory transistor with a memory function in the same way. That is, another information is stored by completely reversing the operating direction of the memory transistor, whereby a so-called two bits/one transistor type high density memory cell can be realized. At present, a silicon nitride film is utilized as a material of the gate insulating film having the discrete traps. As shown in FIG. 5, when a technology feature size is represented by F, a size of a cell including the memory transistors may be regarded as 2F2 per bit while the size is 4F2 per transistor. It can be said that a dramatically high density is realized thereby when it is compared with a conventional flash memory which is said to be suitable for high density while it has a size per bit of 6F2 to 10F2.
Further, FIGS. 6 to 9 show a memory cell array and the erase, program and read operation biases thereof.
As to the erase, FIG. 6 shows word-line page erase and FIG. 7 shows block-area chip erase. The erase is performed in such a manner that a high voltage of 8 V is applied to a bit line diffusion layer, thereby causing so-called band-to-band tunneling and injecting holes. While FIGS. 6 and 7 show that only one of the edges of a channel is erased, it is possible to simultaneously erase both the edges of the channel.
FIG. 8 shows programming. Carriers (electrons), which have been made hot in the channel, are injected in a gate direction at a drain edge and are captured by the discrete traps in a gate insulating film. At this time, since the electrons are injected only into a very small region, charge for detection is approximately one-hundredth that of a conventional flash memory having a conductive poly silicon floating gate in a gate insulation layer as a charge storing section, which leads to reduction of a programming time. Accordingly, even if hot carriers are injected, high speed programming can be realized. Further, the insulating film is less degraded by program by the reduced amount of the injected charge. Furthermore, even if the insulating film is degraded, the charge only leaks from the spatial discrete traps of the portion of the insulating film where the degradation occurs and an amount of stored charge is not influenced thereby. Therefore, it is difficult for data retention characteristics to be subjected to attenuation by programming, whereby the reliability of a nonvolatile memory can be more improved.
Next, FIG. 9 shows a read operation. While read is carried out by detecting an amount of a channel current which depends on whether program is performed or not, an amount of the channel current of a transistor is regulated at a source edge. After all, whether program is carried out or not can be most sensitively detected when read is performed utilizing a side to be detected as a source edge. Therefore, it is preferable to employ reverse read in which a current direction in read is reversed from that during program.
Note that when information of 2 bits is stored in a one transistor type nonvolatile semiconductor memory and the presence or absence of program at both the edges of a channel is detected by reversing the operating direction of the memory each other, there arises a problem in a read margin for identifying a signal for two bits. In read, it cannot be avoided that a current-detection method of determining xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d of the signal by a magnitude of a current is employed and that a signal detection margin is narrowed because information of one of the bits affects a detected current. A report on analysis of the margin is found in Martino Lorenzini et al., xe2x80x9cA Dual Gate Flash EEPROM Cell with Two-Bit Storage Capacityxe2x80x9d, IEEE Transactions on Components, Packaging, and Manufacturing Technology Part A, vol. 20, p 182-189, (1997).
As to program, while the method of injecting charge into the discrete traps in the gate insulating film of a drain side by channel hot electrons was described in FIG. 8, a method of injecting charge to the discrete traps in the gate insulating film of a source side will be described below as another method. An example, in which carrier charge is programmed to the discrete traps in a silicon nitride film by source side injection (SSI), is found in Kuo-Tung Chang et al., xe2x80x9cA New SONOS Memory Using Source-Side Injection for Programmingxe2x80x9d, IEEE Electron Device Letters, vol 19, p 253-255 (1998). FIG. 10 shows a cross section of the device.
The structure of the device is such that a memory transistor is formed on the gate electrode side of a selection transistor by a side wall gate technology. Hot carriers, which have been generated by being accelerated by a drain voltage 5 V in the channel of the selection transistor, behave such that at the moment the hot carriers are injected into the channel of a memory transistor, the hot carriers sense a high electric field (12 V) toward the gate direction at the source side of the memory transistor, are injected in a direction of the gate electrode and are captured by the discrete traps in a gate insulating film. At this time, a gate potential of the selection transistor is set slightly higher (1 V) than a threshold voltage and a channel current is in the saturated region of a low current. The hot carriers generated from a low current are effectively captured by the discrete traps in the gate insulating film. When the source side injection is compared with drain side injection by channel hot electrons as to an amount of channel current necessary to program, an amount of the channel current necessary to program in the source side injection is about one-thirtieth that in the drain side injection whereby reliability can be improved by the reduction of a programming time and an increase in the number of programming so that a programming system by the source side injection is effective. While the selection transistor (switch transistor) must be assembled in a memory cell in the source side injection, a problem resides in that how an increase in cell area can be suppressed.
An example of a memory cell of high density, in which a selection transistor (switch transistor) is assembled in a memory cell, will be described in relation to the present invention. There will be described the 2-bit/cell type high density nonvolatile semiconductor memory device shown in FIG. 11 in in which it is possible for one cell to have information of two bits by a dual way operation and one cell has two memory transistors, one switch transistor, and two diffusion-layer lines. The structure of the memory cell (DSG cell) exemplified in FIG. 11 was made distinct by Yale Ma et al., xe2x80x9cA Dual-Bit Split-Gate EEPROM (DSG) Cell in Contactless Array for Single-Vcc High Density Flash Memoriesxe2x80x9d, IEDM 94, pp 57-60, the proceeding of xe2x80x9cInternational Electron Device Meeting (IEDM)xe2x80x9d, 1994.
The 2-bit/cell type high density nonvolatile semiconductor memory device (DSG cell) shown in FIG. 11 is arranged such that two memory cell transistors having poly-silicon floating gate electrodes 2xe2x80x2-1 and 2xe2x80x2-2 and control gate electrodes 3-1 and 3-2 are formed on a silicon substrate 1, diffusion layers 4-1 and 4-2, which are connected to a source line/bit line, are formed externally of the memory transistors, and a switch transistor, which has a switch gate electrode 8 to be connected to a word line 5, is formed between the two memory transistors. The two memory transistors share the one switch transistor that is formed therebetween by self-aligned diffusion, whereby it is taken into consideration not to increase the area thereof. Since the 2-bit/cell has such a structure that contact holes for metal lines are not formed in a memory cell array, the 2-bit/cell realizes high density with a 1.5 transistor per bit arranged by the self-aligned diffusion.
When the 2-bit/cell type high density nonvolatile semiconductor memory device (DSG cell) carries out program and read to the 2-bit memory in the one cell of FIG. 11, a direction of a current flowing in a channel for one bit is reversed with respect to that for the other bit. Memory information of 2 bits is stored in the different memory transistors. That is, operations for storing 2 bits in one cell are carried out in opposite directions symmetrically. While program: is carried out by a hot carrier programming method, a high electric field can be realized also in a gate direction in addition to a conventional channel direction by the action of the switch transistor, whereby high speed can be realized by program performed by so-called source-side injection.
Further, the 2-bit/cell type high density nonvolatile semiconductor memory device (DSG cell) performs erase by a method of drawing out electrons from floating gate electrodes 2xe2x80x2-1 and 2xe2x80x2-2 by a high electric field applied between the diffusion layers 4-1 and 4-2 for the bit line and the source line that run in parallel with the gate electrodes 3-1 and 3-2 of FIG. 11. As a result, in the memory cell shown in FIG. 11, all the memory cells are erased along the bit line. This state is apparent from FIG. 12 that shows a bias relationship between a selected cell and an unselected cell in the memory cell array. That is, all the memory transistors (A1, C1, B1, and D1) disposed along both the sides of one column of bit lines are simultaneously erased so that programming cannot be carried out in a bit unit or a byte unit and erase is carried out in block-area.
A dramatically high degree of density is proposed by the memory cell (NROM) shown in FIGS. 3 to 5. In the memory cell, while necessary charge for program is reduced to about one-hundredth conventional one because the discrete traps in an insulating film are utilized. However, since program is carried out by channel hot carrier injection, a necessary program current is about 30 times source side injection. Further, disturb is applied to an unselected cell as read is accumulated, whereby a signal margin is liable to be deteriorated. Furthermore, as can be understood from a bias relationship in a memory cell array shown in FIGS. 6 to 9, since a virtual ground system, in which operation is carried out by interchanging a source line and a bit line, is employed, there is a possibility that even a surface current which is transmitted on the surface of a semiconductor is detected in addition to a channel current detected through a predetermined channel particularly during read.
FIG. 10 shows a memory transistor employing source side injection in which discrete traps in a gate insulating film are utilized. While the figure shows up to that a one-way operation method is employed with a source/drain fixed, it is not clarified how an actual memory cell array is organized.
In the memory cell (DSG) shown in FIGS. 11 and 12, since the gate electrode of a memory transistor runs in parallel with a source line/bit line as described in Description of Prior Art, it is impossible to perform word-line erse. Further, the conductive floating gate electrodes 2xe2x80x2-1 and 2xe2x80x2-2 serving as store areas include electrodes which are arranged independently of other memory cells.
Furthermore, in the memory cell of FIG. 11, the gate electrode 3-1 and 3-2 of the memory transistor are lined so as to cover the floating gate electrodes 2xe2x80x2-1 and 2xe2x80x2-2. As a result, a word line 5 which is across on the gate electrodes and the floating gate electrodes 2xe2x80x2-1 and 2xe2x80x2-2 cannot be subjected to stacked film processing utilizing self-aligned diffusion. Thus, the word line 5 must be stacked on the floating gate electrodes 2xe2x80x2-1 and 2xe2x80x2-2 by means of process alignment, whereby an area is increased by an alignment accuracy. It is reported that when a technology feature size is represented by xe2x80x9cFxe2x80x9d, a cell area per bit of the memory cell of FIG. 11 is 5.4F2 as a result of an increase in area due to the alignment accuracy. While the memory cell of FIG. 11 realizes high density, its area is increased by 35% as compared with a memory cell having an area of 4F2 because it requires no alignment in processing.
Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit having a nonvolatile memory which has less possibility of detecting a surface current other than a channel current detected through a predetermined channel.
Another object of the present invention present invention is to make it possible to carry out word-line erase in multi-storage nonvolatile memory cells.
Still another object of the present invention is to provide a semiconductor integrated circuit capable of realizing multi-storage nonvolatile memory cells while suppressing an increase in chip area.
The present invention intends to provide a semiconductor integrated circuit having a nonvolatile semiconductor memory of high density, high speed and high reliability.
These and other objects and novel features of the present invention will become more apparent from following description of the specification taken in conjunction with the accompanying drawings.
The embodiments of the present invention disclosed in this application mainly have the following features.
That is, since a gate insulating film having discrete traps is used, a multi-storage cell is organized such that one memory transistor can store information of at least two bits by local programming, whereby stored charge for detection can be dramatically reduced as compared with that of conductive floating gate electrodes.
Since program is performed utilizing at least source side injection, a programming efficiency is increased as compared with that of channel hot electron drain side injection, a channel current necessary to program is reduced, and the number of programmable bits is increased, whereby a chip program time is reduced and the programmable number of times is increased.
A switch transistor, which is necessary to realize the source side injection, is formed in a memory cell together with a memory transistor by self-aligned diffusion, thereby suppressing an increase in area. Further, the line of the switch transistor is devised to shut off the flow of a surface current, which is flown due to a virtual ground, to a source line/bit line.
At least word-line program is permitted by connecting the gate electrode of the memory transistor to a word line.
In a memory cell including the memory transistor and the switch transistor, there is employed a method of drawing out stored charge to the memory gate electrode side of the memory transistor, that is, to the word line side as a method of securing the data retention characteristics of stored charge which is programmed by the source side injection and allowing erase. For this purpose, as to thicknesses of silicon oxide films disposed above and below the gate insulating film having the discrete traps, that is, a silicon nitride film, a thickness of the lower (bottom) oxide film is made thicker than that of the upper (top) oxide film.
The structures of several types of memory cells according to the embodiments of the present invention will be exemplified here. A first memory cell structure is such that each of memory cells includes one memory transistor, two switch transistors and two diffusion-layer lines. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode connected to a word line, the two diffusion-layer lines constitute a source line and a bit line, and the switch gate electrodes of the two switch transistors are extended along the source line and the bit line.
A second memory cell structure is such that each of memory cells includes one memory transistor, two switch transistors and two transistor inversion-layer lines. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode connected to a word line, the two transistor inversion-layer lines constitute a source line and a bit line, and the two switch transistors and the two transistor no inversion-layer lines constituting the source line and the bit line share the memory gate electrode, respectively.
A third memory cell structure is such that each of memory cells includes one memory transistor, one switch transistor, one transistor inversion-layer line and one diffusion-layer line. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode connected to a word line, the one transistor inversion-layer line constitutes a source line, the one diffusion-layer line constitutes a bit line, and the one switch transistor and the one transistor inversion-layer line constituting the source line share the transistor gate electrode, respectively.
A fourth memory cell structure is such that each of memory cells includes two memory transistors, one switch transistor and two diffusion-layer lines.
Each of the memory transistors includes a gate insulating film having discrete traps and a transistor gate electrode connected to a word line, the two diffusion-layer lines constitute a source line and a bit line, and the switch gate electrode of the one switch transistor is extended along the source line and the bit line.